Signal Integrity — High-Speed PCB Design

Signal integrity (SI) is the study of how electrical signals behave as they travel through PCB transmission lines, connectors, and cables. At high data rates (>100 Mbps), signal degradation from reflections, crosstalk, impedance discontinuities, and losses can cause bit errors. SI engineering prevents these issues through controlled impedance design, termination, and routing discipline.

Why companies use it

·Modern digital interfaces (PCIe, USB 3, DDR5, Ethernet) require controlled impedance PCBs — without SI analysis, high-speed designs fail
·Signal integrity simulation prevents costly PCB spins — catching reflections or crosstalk in simulation is far cheaper than discovering them in hardware
·Signal integrity constraints drive PCB stack-up, trace width, via design, and component placement — SI must be considered from the beginning of layout
·Data centre and communications equipment manufacturers face strict SI budgets where every connector and via must be characterised

What hiring managers look for

·High-speed PCB design is a specialised skill that separates senior from junior PCB design engineers
·SI simulation experience (HyperLynx, ADS, SI9000, HFSS) is directly practical in high-speed electronics roles
·Understanding the physical cause of reflections (impedance mismatch), crosstalk (coupling), and loss (skin effect, dielectric loss) shows depth
·Candidates who have debugged real SI problems using oscilloscopes, TDR, and eye diagrams are highly valued

Typical interview questions

What causes reflections on a PCB trace and how do you prevent them?

What is the skin effect and how does it affect high-speed signal transmission?

How do you calculate the characteristic impedance of a microstrip trace?

What is an eye diagram and what does a closed eye indicate?

How do differential pairs on a PCB reduce electromagnetic interference (EMI)?

Common mistakes

·Breaking differential pairs at layer transitions without tight via spacing — the impedance discontinuity at the via creates reflections
·Running high-speed signals across split power planes — the return current cannot follow the signal path and creates EMI
·Not specifying impedance-controlled layers when sending PCB files to the fabricator — the fabricator will use standard trace widths that may not meet impedance targets
·Placing decoupling capacitors too far from the power pins of high-speed ICs — at GHz frequencies, even 1 mm of trace adds significant inductance
·Over-terminating or under-terminating transmission lines — series termination, parallel termination, and AC termination each suit different scenarios

Real engineering example

A PCIe Gen 4 board design was passing compliance tests on 8 of 16 lanes but failing on the remaining 8. TDR measurements revealed that the failing lanes had 8–12% higher characteristic impedance than specified (100 Ω ±10%). PCB cross-section analysis showed that the dielectric thickness in the failing lanes was 12 µm thicker than in the passing lanes — a lamination pressure non-uniformity. Tighter fabrication tolerances on the internal layer dielectric thickness resolved the impedance variation and brought all 16 lanes into compliance.

Topics covered

signal integrityPCBimpedancehigh-speeddifferential pairseye diagramTDRPCIe