Process Engineer (Semiconductor) Interview Guide

Process module ownership: lithography, etch, deposition (CVD/PVD/ALD), CMP, diffusion, or implant

Statistical Process Control (SPC) and yield analysis — quantify yield improvements you have driven

Failure analysis skills: cross-section SEM, EDX, TEM sample preparation, root-cause methodology

Design of Experiments (DoE) for process optimisation — mention the specific methodology (Taguchi, RSM, full factorial)

Cleanroom experience and knowledge of contamination control protocols

Process integration awareness: understanding how your module interacts with adjacent process steps

Process ownership — do you understand your process deeply enough to troubleshoot it at 2am without the process recipe in front of you?

Yield focus — can you analyse wafer maps, correlate with process history, and find root cause in data?

Cross-functional effectiveness — process engineering requires constant collaboration with equipment, integration, and yield engineering

Experimental design skills — can you design a DOE that efficiently identifies the critical process variables?

Safety in a hazardous chemical environment — semiconductor processes involve toxic, flammable, and corrosive chemicals

Listing process steps without stating the technology node or product type (logic, DRAM, analogue, power)

No yield or throughput numbers — these are the language of fab management

Omitting equipment experience: tool types and vendors matter (Applied Materials, Lam Research, ASML, TEL)

Academic experience presented without clarity on whether it was research-grade or production-like conditions

Q1

Walk me through how you would investigate a sudden yield drop on your process layer.

Q2

Describe a process optimisation project you led. What was the metric you were improving and how did you approach it?

Q3

How do you design a Design of Experiments (DOE) to optimise a deposition process?

Q4

What is the difference between Cpk and Ppk and which would you use to characterise a new process?

Q5

How do you manage process qualification when equipment is shared between multiple product flows?

State the technology node prominently: 180nm, 90nm, 28nm — it anchors your experience immediately

Frame each role around a yield or cycle-time improvement with before/after numbers

If you have transferred a process from R&D to production, describe that explicitly — it is highly valued

TSMC-bound candidates should emphasise high-volume manufacturing discipline and statistical rigor over innovation