DFT — Design for Testability

Design for Testability (DFT) is the practice of designing electronics so that manufacturing defects can be efficiently detected and located during production test. It covers bed-of-nails (ICT) access, JTAG boundary scan, built-in self-test (BIST), test point placement, and functional test connector provision.

Why companies use it

·Products without adequate test access ship with undetected defects — DFT reduces field returns
·ICT (In-Circuit Test) can test 95%+ of component and solder defects in seconds, but only if test points are available
·The cost of detecting a defect increases by orders of magnitude as it progresses from ICT to functional test to field return
·JTAG boundary scan enables cluster testing of high-density PCBs where physical test probe access is limited

What hiring managers look for

·Electronics engineers who design for testability save significant manufacturing cost — this is directly visible on the production line
·Understanding the trade-offs between test coverage, test cost, and board density shows design maturity
·Knowledge of ICT programming, boundary scan (JTAG/IEEE 1149.1), and flying probe testing shows depth across test modalities
·DFT is increasingly important as board density increases and physical test access decreases

Typical interview questions

What is the difference between ICT (In-Circuit Test) and functional test? What defects does each catch?

What is a bed-of-nails test fixture and what are its limitations?

How does JTAG boundary scan work and when would you use it instead of ICT?

What are the minimum DFT requirements for an ICT-testable PCB?

How do you test a PCB when there is no physical probe access to critical nodes?

Common mistakes

·Routing critical signals underneath BGA or QFN components with no via access — the ICT cannot probe them and they become untestable
·Placing test points on only one side of the board when the fixture can only access one side — SMT components on the top side may need top-side test points
·Using test points smaller than 0.9 mm diameter — smaller test points have poor probe contact reliability in a fixture
·Not including a programming header or JTAG connector on the PCB for firmware loading and boundary scan
·Assuming flying probe testing compensates for poor DFT — flying probe is slow and expensive at volume; ICT is the preferred production test method

Real engineering example

A medical device manufacturer found that their new PCB had only 42% ICT fault coverage because 28 critical signal nets were routed under BGA packages with no test point vias. Functional test could catch gross faults, but not intermittent solder defects. After a field return analysis attributed 65% of returns to BGA solder joint defects that had passed functional test, the PCB was redesigned with test via access, bringing ICT coverage to 91%. Field returns dropped by 58% on the next production revision.

Topics covered

DFTdesign for testICTJTAGboundary scantest coveragePCBelectronics