Lithography — Patterning at the Nanoscale

Lithography is the process of transferring a circuit pattern onto a wafer surface using light (or extreme ultraviolet radiation). A photoresist layer is exposed through a mask (reticle), then developed to create the pattern, which is then etched or implanted to form transistors and interconnects. EUV lithography at 13.5 nm wavelength enables features below 10 nm.

Why companies use it

·Lithography defines the critical dimensions of transistors — smaller features enable more powerful, energy-efficient chips
·The dominant manufacturing bottleneck in semiconductor: yield and throughput of the lithography scanner determines the fab's capacity
·ASML's EUV scanners (used by TSMC, Samsung, Intel) are the only tools capable of printing sub-7nm features at volume
·Improving overlay accuracy and reducing line edge roughness (LER) in lithography directly improves device performance and yield

What hiring managers look for

·Lithography engineers at ASML, TSMC, and Intel are among the most specialised in the industry — deep knowledge commands premium compensation
·Understanding the relationship between numerical aperture (NA), wavelength, and resolution is the foundation of lithography engineering
·Process engineers need to understand resist chemistry, exposure dose, and focus to optimise lithography processes
·Equipment engineers in this area need to understand optical alignment, vibration isolation, and thermal management at angstrom scale

Typical interview questions

Explain the Rayleigh criterion and how it determines the resolution of a lithography tool.

What is the difference between DUV (deep ultraviolet) and EUV lithography? Why did the industry transition to EUV?

What is overlay error and why does it matter for multi-patterning processes?

How does immersion lithography extend DUV resolution capability?

What are the main challenges in EUV lithography at the system and process level?

Common mistakes

·Confusing resolution (smallest printable feature size) with overlay (alignment accuracy between layers) — both are critical, but they are independent performance parameters
·Not accounting for the resist contribution to line edge roughness — the photoresist is not a perfect medium
·Assuming EUV eliminates multi-patterning — for the smallest features, multiple EUV exposures (SAQP) are still required
·Underestimating the mechanical complexity: a modern EUV scanner positions the wafer stage to sub-nanometre accuracy at 300 mm/s scan speed
·Ignoring the stochastic effects at EUV: at 13.5 nm wavelength, photon shot noise is a fundamental limit to pattern fidelity

Real engineering example

During qualification of a new EUV process node at a leading-edge fab, yield was 20 percentage points below target due to local critical dimension uniformity (LCDU) failures on dense line-space patterns. Systematic analysis showed that resist sensitivity variation across the wafer was amplifying dose non-uniformity from the illumination system. By tuning the dose-focus matrix and implementing a wafer-level correction in the exposure recipe, LCDU improved from 3.2 nm to 1.8 nm 3σ, recovering 18 percentage points of yield.

Topics covered

lithographyEUVDUVASMLphotoresistresolutionnanoscalesemiconductor