PECVD — Plasma-Enhanced Chemical Vapour Deposition

PECVD uses plasma energy to enable chemical vapour deposition at lower temperatures than thermal CVD, making it compatible with temperature-sensitive layers in the back-end-of-line (BEOL) process. It is the primary technique for depositing dielectric films (SiO₂, Si₃N₄, SiON, low-κ dielectrics) in semiconductor manufacturing.

Why companies use it

·Lower deposition temperature (200–400°C versus 700°C+ for thermal CVD) protects underlying metal layers in BEOL processing
·Wide range of film properties accessible by tuning plasma parameters (frequency, power, pressure, gas ratio)
·High deposition rates enable cost-effective thick dielectric layers for interlayer dielectric (ILD) and passivation
·Essential for depositing advanced low-κ (κ < 2.5) dielectric films for high-speed interconnects

What hiring managers look for

·PECVD is one of the most commonly used deposition techniques in semiconductor fabs — process engineers are expected to understand it deeply
·Film stress control is a critical PECVD parameter — uncontrolled stress causes wafer bow, die cracking, and delamination
·Understanding the relationship between plasma parameters and film properties (stress, wet etch rate, refractive index) is essential for process development
·Particle management in PECVD chambers is a constant challenge — engineers who understand chamber conditioning and particle sources are valued

Typical interview questions

How does plasma activation enable PECVD to operate at lower temperatures than thermal CVD?

What is the typical structure of a PECVD chamber and what does each component do?

How do you tune PECVD SiN film stress from compressive to tensile?

What is a PECVD wet etch rate (WER) and why is it used as a film quality indicator?

How do you manage particle contamination in a PECVD chamber after extended use?

Common mistakes

·Not characterising film stress alongside thickness — a SiN film deposited for etch stop duty must also be in the right stress state for the subsequent CMP step
·Assuming that film composition is constant throughout deposition — initial nucleation conditions can create interface layers with different properties
·Underestimating plasma non-uniformity across the wafer — edge-to-centre film thickness variation is a common source of within-wafer non-uniformity
·Ignoring chamber wall effects — polymer and by-product deposition on chamber walls changes plasma characteristics over time
·Not establishing a chamber seasoning procedure — a freshly cleaned chamber behaves differently from a conditioned chamber

Real engineering example

A BEOL process team found that inter-metal dielectric CMP yield was degrading over 500 wafer runs. Investigation correlated the degradation with increasing PECVD SiO₂ deposition rate and higher film porosity (measured by WER increase). Root cause: fluorine contamination from previous TEOS-based cleans had incorporated into the SiO₂ network, increasing its porosity and WER. A chamber clean and recondition protocol, implemented every 200 wafers, stabilised WER and recovered CMP yield.

Topics covered

PECVDCVDplasmathin filmdielectricBEOLsemiconductordeposition